1. Technical Field
The present invention relates to a body biasing structure for SOI (Silicon-On-Insulator) devices, and more specifically to a body biasing structure of devices connected in series on an SOI substrate.
2. Description of Related Art
SOI technology, which consists of forming a single-crystal-silicon layer on an insulator layer and then forming devices on the silicon layer, has been utilized recently to cope with increasing demands for faster, less power consuming and more highly integrated semiconductor integrated circuits.
SOI technology can decrease the electrical resistance between devices and increase their heat efficiency, and it is useful for high-speed semiconductor devices with small electrical power consumption. Also, it is possible to speed up a device more than 30% and decrease the amount of electrical power consumption of the device about 30%. Further, it is easier to realize System on Chip (SoC) technology because electrical isolation between devices is easier.
Therefore, research has been actively proceeding on memory devices using an SOI substrate.
FIG. 1 is the structure of a conventional MOSFET fabricated on an SOI substrate. The SOI MOSFET includes a buried oxide layer 11), a source region 22, a drain region 24, a body region 26, a gate insulating layer 30, and a gate 40. The supporting substrate for the SOI device is not shown.
An SOI MOSFET, in a conventional operating condition, can be divided into two cases. In the first case, the silicon body of FIG. 1 is fully depleted Full Depletion, hereinafter referred to as ‘FD’) and in the other case, the silicon body is partially depleted (Partial Depletion, hereinafter referred to as ‘PD’). In each case, the SOI MOSFET exhibits different operating characteristics.
For convenience, only an SOI nMOSFET device is described in detail herein. However, an SOI MOSFFT device can be understood the same way except for replacing “n-type” and “electron” with “p-type” and “hole” respectively.
Although a device on an SOI substrate has many strong points as mentioned before, it also has a weak point during operation because the source region 22 and the drain region 24 make the silicon body 26 float electrically, as shown in FIG. 1.
That is, in a conventional bulk MOSFET, when too high of a voltage is applied to the drain region 24, holes generated by an ionized collision from the drain region 24 can escape through the substrate. But in an SOI MOSFET, the holes can not escape through the substrate due to the floating body 26, so the holes must escape through the source region 22. As a result, the holes that have not escaped become accumulated on the floating body 26 near the source region 22. This increases the electric potential of the floating body 26, and the increased electric potential decreases the threshold voltage and triggers a kink effect. The kink effect is shown by a sudden rise in drain current even before the breakdown voltage is reached. Kink effects are more prevalent in the PD structure than in the FD structure. This results from the fact that in the PD structure, the electric potential of the floating body region 26 is relatively lower than that of the depletion region, and holes are held in the body region, while in the FD structure, the distribution of electric potential at the depletion region makes holes escape easily toward the source region 22.
FIGS. 2a, 2b and 2c show simulation results comparing the operational characteristics of the SOI nMOSFET with the conventional bulk nMOSFET under the same manufacturing conditions. FIG. 2a is a graph illustrating the electrical characteristics ID-VD (VG=1.1˜7.7V, step=1.1V) of the conventional bulk nMOSFET. FIG. 2b shows the kink effect (VG=1.1˜3.3V, step=1.1V) of the SOI nMOSFET, and FIG. 2c is a graph illustrating the electrical characteristics ID-VD (VG=1.1˜7.7V, step=1.1V) of the SOI nMOSFET.
As mentioned above, the effect of hole accumulation on the device features can be not only the kink effect (as shown in FIG. 2b) but also a decrease in the drain breakdown voltage (as shown in FIG. 2c). Due to the floating body effect, the electric potential of the body can rise more easily than in the conventional bulk MOSFET, and this accelerates the undesired operation as a parasitic bipolar junction transistor when the junction between the source region and the body region is biased more forwardly.
In the FD structure, it is advantageous that kink effects are smaller than in the PD structure. However, at a high drain voltage, similar to the PD structure, hole accumulation at the depletion region adjacent to the source region causes a lower drain voltage.
Therefore, it is most important to suppress the floating body effect as described above by body biasing in the SOI technology.
Body biasing is achieved in one conventional method as shown in FIG. 3. Poly-silicon has been patterned as a gate over a P-type silicon active region. N+ and P+ ions have been injected, a contact has been made on the silicon region injected with P+ ions, and a bias has been added there. Through the silicon active region under the poly-silicon, an active region, which can be a channel for operating a device, has been biased.
However, according to the conventional method, in order to bias along with an active region under a gate, it has been necessary to define an active region along with a gate line up to a region, at which a contact can be formed, and it is difficult to define an arranged active region under a gate line accurately when the width of the gate line is narrow. Moreover, in a case where many devices are connected in series, there is a need to body bias all devices, and so this has been a disadvantage for increasing device integration.
Especially susceptible to these problems are various series circuits of devices, which have a source/drain in common. Typical examples of series circuits are NANDgates and NORgates, which are fundamental in digital logic circuits, and NAND type flash memories, which have gained popularity as information storing devices in conjunction with a sudden increase in consumption of multi-media instruments, etc. In a NAND gate circuit, nMOSFETs are connected in series, and in a NOR gate circuit, pMOSFETs are connected in series. In a NAND type flash memory, usually 8 to 32 nMOSFET type memory cells are connected in series.
To suppress the floating body effect, there have been various methods attempted, such as forming an SOI device at a full depletion layer, forming a back-channel gate, connecting an SOI body to a silicon supportive substrate, forming a hetero junction, and so on. Each method has had its own problems; in a method for forming an SOI device at a full depletion layer, there was a limitation on the thickness of the silicon layer on the SOI substrate, and the SOI device characteristics were so heavily dependent on the uniformity of the silicon layer that poor uniformity could cause malfunctions; in a method to form a back channel gate or to form a hetero junction, such particulars as the SOI structure, the arrangement of contacts, the resistance and so on, have to be taken into consideration, and there are problems with contacts when a channel is too broad or too short, and from a view of the process, it is difficult to embody the contact, which connects a SOI body to a silicon supportive substrate.